A first conventional serial-parallel type A/D converter comprises a recursive circuit consisting of a first sample holding circuit for sampling and holding an analogue signal, a 4-bit parallel A/D converter which converts the analogue signal to a 4-bit digital code number, a digital/analogue (D/A) converter which converts the 4-bit digital code number to an analogue signal, a subtracter which subtracts the converted analogue signal from the sampled analogue signal and amplifies the result of subtraction by four times, a second sample holding circuit for sampling and holding an output signal of the subtracter and amplifies the sampled signal by twice, and a switch which selectively connects inputs of the 4-bit parallel A/D converter and the first sample holding circuit with either an input terminal of the serial-parallel type A/D converter to which an original input analogue signal is supplied or an output of the second sample holding circuit.
In operation, in the first cycle, the switch connects terminals so that the input analogue signal is supplied to both the first sample holding circuit and the 4-bit parallel A/D converter. The sample holding circuit samples the input analogue signal to hold the sampled input signal for a predetermined period. The 4-bit parallel A/D converter converts the input analogue signal to a first 4-bit digital code number corresponding to first highest significant bits of the sampled input analogue signal. Then, the D/A converter converts the first 4-bit digital code number to an analogue signal which corresponds to the first highest significant bits of the sampled input analogue signal. Then, the subtracter subtracts the converted analogue signal form the the sampled input analogue signal and amplifies the result of subtraction by four times. The second sample holding circuit samples an output signal of the subtracter and amplifies the sampled output signal by twice and holds the amplified result for a predetermined period. As a result, the second sample holding circuit generates an output signal which is an amplified value by eight times of the result of subtraction of the analogue signal supplied by the D/A converter from the sampled input analogue signal.
Next, in the second to fourth cycles, the switch connects terminals so that an output of the second sample holding circuit is supplied to inputs of the first sample holding circuit and the 4-bit parallel A/D converter. Then, the same converting operation of the first cycle described above is carried out in the second to fourth cycles to obtain second to fourth 4-bit digital code numbers corresponding to second to fourth highest significant bits of the sampled input analogue signal, respectively.
By carrying out the converting operations of the first to fourth cycles described above, the first to fourth 4-bit digital code numbers respectively corresponding to the first to fourth highest significant bits of the input analogue signal can be obtained, provided that the four 4-bit digital code numbers overlap at the most and least significant bits of the adjacent code numbers by one bit, so that the resultant digital code number which corresponds to the original input analogue signal is a 13-bit digital code number in accordance with the bit combination of (4.times.4-3 bits).
A second conventional serial-parallel type A/D converter comprises first to third circuit blocks serially connected and a 4-bit parallel A/D converter serially connected to an output of the third circuit block. Each of the first to third circuit blocks comprises a first sample holding circuit which samples and holds an input analogue single, a 4-bit parallel A/D converter which converts the input analogue signal to a 4-bit digital code number, a D/A converter which converts the 4-bit digital code number to an analogue signal, a subtracter which subtracts the converted analogue signal from the sampled input analogue signal and amplifies the result of subtraction by four times, and a second sample holding circuit which samples an output of the subtracter and amplifies the sampled signal by twice and holds the amplified value.
Outputs of the first and second circuit blocks are respectively supplied to inputs of the second and third circuit blocks, and the output of the third circuit block is supplied to an input of the 4-bit parallel A/D converter.
In operation, the same converting operation as that in each cycle of the first conventional serial-parallel type A/D converter is carried out in each of the first to third circuit blocks sequentially, and first to fourth 4-bit digital code numbers respectively corresponding to first to fourth highest significant bits of the input analogue signal can be obtained in the first to third circuit blocks and the 4-bit A/D converter connected to the third circuit block, respectively, in pipe lining operation. Thus, a 13-bit digital signal is generated by the bit combination as described in the first conventional serial-parallel type A/D converter.
According to the first and second conventional serial-parallel type A/D converters, however, there are disadvantages as described after.
In the first conventional serial-parallel type A/D converter, the operation time for obtaining the 13-bit digital code number corresponding to the input analogue signal is relatively long, because the four cycles must be carried out to convert the input analogue signal to the digital code number. The operation time of one cycle depends on the precision of A/D conversion, so that it is difficult to shorten the converting operation time without reducing the precision of A/D conversion which is of 13 bits in the first conventional serial-parallel type A/D converter.
In the second conventional serial-parallel type A/D converter, the converting operation time is approximately one fourth of that in the first conventional serial-parallel type A/D converter, however, a chip area and a power consumption of the converter are four times of those of the first conventional serial-parallel type A/D converter.